(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for improving the height of an interconnect bump for small pad design.
(2) Description of the Prior Art
Continued decrease in semiconductor device feature size has led to a significant increase in semiconductor device density, which places increased emphasis on device or package I/O capabilities. The metal connections, which connect the Integrated Circuit to other circuits or to system components, have therefore become more important and can, with further miniaturization of the semiconductor device, have an increasingly negative impact on circuit performance.
One of the approaches that has been taken to solve these packaging problems is to design chips and chip packaging techniques that offer dependable methods of increased interconnecting of chips at a reasonable manufacturing cost. This has led to the development of Flip Chip Packages.
Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads on the chips and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest paths. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger, and to more sophisticated substrates that accommodate several chips to form larger functional units.
The flip-chip technique, using an array of I/O interconnects, has the advantage of achieving the highest density of interconnection to the device combined with a very low inductance interconnection to the package. Prior Art substrate packaging uses ceramic and plastic flip chip packaging. Ceramic substrate packaging is expensive and has proven to limit the performance of the overall package. Recent years has seen the emergence of plastic substrate flip chip packaging, this type of packaging has become the main-stream design and is frequently used in high volume flip chip package fabrication. The plastic substrate flip chip package performs satisfactorily when used for low-density flip chip Integrated Circuits (IC's). If the number of pins emanating from the IC is high, that is in excess of 350 pins, or if the number of pins coming from the IC is less than 350 but the required overall package size is small, the plastic flip chip structure becomes complicated and expensive. This multi-layer structure results in a line density within the package of typically a 2-3 mil range. This line density is not sufficiently high for realizing the fan-out from the chip I/O to the solder balls on the package within a single layer, leading to the multi-layer approach. The multi-layer approach brings with it the use of relatively thick (50 to 75 μm) dielectric layers, these layers have a Coefficient of Thermal Expansion (CTE) that is considerably higher than the CTE of the laminate board on which the plastic flip chip package is mounted. To counteract this difference in the CTE, the overall package must be (thermally and mechanically) balanced resulting in the use of additional material and processing steps to apply these materials, increasing the cost of the Ball Grid Array (BGA) package and creating a yield detractor.
In creating semiconductor devices, the technology of interconnecting devices and device features is a continuing challenge in the era of sub-micron devices. Bond pads and solder bumps are frequently used for this purpose, whereby continuous effort is dedicated to creating bond pads and solder bumps that are simple, reliable and inexpensive. The invention provides a method of creating solder bumps of increased height, thereby improving interconnect reliability while not adding to the processing cost of creating the interconnect bumps.
U.S. Pat. No. 5,543,253 (Park et al.) shows a dual damascene like Photo process for a T-gate.
U.S. Pat. No. 6,042,996 (Lin et al.) shows a dual damascene process.
U.S. Pat. No. 6,232,212 (Degani et al.), U.S. Pat. No. 6,153,503 (Lin et al.), U.S. Pat. No. 6,130,141 (Degani et al.) and U.S. Pat. No. 6,118,180 (Loo et al. show related Bump and UBM processes.